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74LVC3GU04DCURG4

  • Available: 12334

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Description
General description
The 74LVC3G04 provides three inverting buffers.Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in a mixed 3.3 V and 5 V environment.This device is fully specified for partial power-down applications using IOFF.
The IOFF circuitry disables the output, preventing a damaging backflow current through the device when it is powered down.
Features
• Wide supply voltage range from 1.65 V to 5.5 V
• 5 V tolerant outputs for interfacing with 5 V logic
• High noise immunity
• Complies with JEDEC standard: ◆ JESD8-7 (1.65 V to 1.95 V) ◆ JESD8-5 (2.3 V to 2.7 V) ◆ JESD8B/JESD36 (2.7 V to 3.6 V)
• ESD protection: ◆ HBM JESD22-A114E exceeds 2000 V ◆ MM JESD22-A115-A exceeds 200 V
• ±24 mA output drive (VCC = 3.0 V)
• CMOS low power consumption
• Latch-up performance exceeds 250 mA
• Direct interface with TTL levels
• Multiple package options
• Specified from −40 °C to +85 °C and −40 °C to +125 °C
Alternatives

Functional Equivalent (FE) materials, including Fused Filament Fabrication (FFF) form, assembly, and functionally compatible substitute materials.

SHIPPING GUIDE

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