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A3P250L-VQG100I
- Manufacturer's Part No.:A3P250L-VQG100I
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- Series:ProASIC3L
- Description:IC FPGA 68 I/O 100VQFP
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- Quantity:RFQAdd to RFQ List
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- In Stock: 9559
- Price: please call
- Available: 9559
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- Description
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These features enable designers to create high-density systems using existing ASIC or FPGA design flows and tools.
Features and BenefitsHigh Capacity
• 30 k to 1 Million System Gates
• Up to 144 kbits of True Dual-Port SRAM
• Up to 300 User I/OsReprogrammable Flash Technology
• 130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS Process
• Live at Power-Up (LAPU) Level 0 Support
• Single-Chip Solution
• Retains Programmed Design when Powered OffOn-Chip User Nonvolatile Memory
• 1 kbit of FlashROM with Synchronous InterfacingHigh Performance
• 350 MHz System Performance
• 3.3 V, 66 MHz 64-Bit PCI (except A3P030)In-System Programming (ISP) and Security
• Secure ISP Using On-Chip 128-Bit Advanced Encryption Standard (AES) Decryption (except A3P030 and ARM®- enabled ProASIC®3 devices) via JTAG (IEEE 1532– compliant)
• FlashLock® to Secure FPGA ContentsLow Power
• Core Voltage for Low Power
• Support for 1.5-V-Only Systems
• Low-Impedance Flash SwitchesHigh-Performance Routing Hierarchy
• Segmented, Hierarchical Routing and Clock Structure
• Ultra-Fast Local and Long-Line Network
• Enhanced High-Speed, Very-Long-Line Network
• High-Performance, Low-Skew Global Network
• Architecture Supports Ultra-High UtilizationAdvanced I/O
• 700 Mbps DDR, LVDS-Capable I/Os (A3P250 and above)
• 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation
• Bank-Selectable I/O Voltages—Up to 4 Banks per Chip
• Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V / 2.5 V / 1.8 V / 1.5 V, 3.3 V PCI / 3.3 V PCI-X (except A3P030), and LVCMOS 2.5 V / 5.0 V Input
• Differential I/O Standards: LVPECL, LVDS, BLVDS, and M-LVDS (A3P250 and above)
• I/O Registers on Input, Output, and Enable Paths
• Hot-Swappable and Cold Sparing I/Os (A3P030 only)
• Programmable Output Slew Rate (except A3P030) and Drive Strength
• Weak Pull-Up/Down
• IEEE 1149.1 (JTAG) Boundary Scan Test
• Pin-Compatible Packages Across the ProASIC3 FamilyClock Conditioning Circuit (CCC) and PLL (except A3P030)
• Six CCC Blocks, One with an Integrated PLL
• Configurable Phase-Shift, Multiply/Divide, Delay Capabilities and External Feedback, Multiply/Divide, Delay Capabilities, and External Feedback
• Wide Input Frequency Range (1.5 MHz to 350 MHz)
• CoreMP7Sd (with debug) and CoreMP7S (without debugSRAMs and FIFOs (except A3P030)
• Variable-Aspect-Ratio 4,608-Bit RAM Blocks (×1, ×2, ×4, ×9, and ×18 Organizations Available)
• True Dual-Port SRAM (except ×18)
• 24 SRAM and FIFO Configurations with Synchronous Operation up to 350 MHzSoft ARM7™ Core Support in M7 ProASIC3 Devices
• CoreMP7Sd (with debug) and CoreMP7S (without debug)
Functional Equivalent (FE) materials, including Fused Filament Fabrication (FFF) form, assembly, and functionally compatible substitute materials.
SHIPPING GUIDE
Shipping Methods
Rest assured that your orders will be handled by these trusted providers, such as DHL, FedEx, SF, and UPS.
Shipping Cost
Shipping starts at $40 but varies for destinations like South Africa, Brazil, India, and more. The actual shipping charges depend on time zone, country, and package weight/volume.
Delivery Time
We ship orders once daily, around 5 p.m., except on Sundays. The estimated delivery time may vary depending on the courier service you choose, but typically ranges from 5 to 7 business days.
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