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A3PE1500-FGG484I
- Manufacturer's Part No.:A3PE1500-FGG484I
- Manufacturer:
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- Series:ProASIC3E
- Description:IC FPGA 280 I/O 484FBGA
- Datasheet:
- Quantity:RFQAdd to RFQ List
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- Delivery:
- Available: 575
Reference Price(In US Dollars)
Qty | Unit Price | Ext.Price |
---|---|---|
1+ | US $243.64950 | US $243.65 |
10+ | US $211.16290 | US $2111.63 |
30+ | US $191.67094 | US $5750.13 |
100+ | US $175.42764 | US $17542.76 |
500+ | US $170.55465 | US $85277.33 |
1000+ | US $162.43300 | US $162433.00 |
Do you want a lower wholesale price? Please send us an inquiry, and we will respond immediately.
- Description
- Alternatives
- Shopping Guide
These features enable designers to create high-density systems using existing ASIC or FPGA design flows and tools.
Features and BenefitsHigh Capacity
• 600 k to 3 Million System Gates
• 108 to 504 kbits of True Dual-Port SRAM
• Up to 620 User I/OsReprogrammable Flash Technology
• 130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS Process
• Instant On Level 0 Support
• Single-Chip Solution
• Retains Programmed Design when Powered OffOn-Chip User Nonvolatile Memory
• 1 kbit of FlashROM with Synchronous InterfacingHigh Performance
• 350 MHz System Performance
• 3.3 V, 66 MHz 64-Bit PCIIn-System Programming (ISP) and Security
• ISP Using On-Chip 128-Bit Advanced Encryption Standard (AES) Decryption via JTAG (IEEE 1532–compliant)
• FlashLock® Designed to Secure FPGA ContentsLow Power
• Core Voltage for Low Power
• Support for 1.5-V-Only Systems
• Low-Impedance Flash SwitchesHigh-Performance Routing Hierarchy
• Segmented, Hierarchical Routing and Clock Structure
• Ultra-Fast Local and Long-Line Network
• Enhanced High-Speed, Very-Long-Line Network
• High-Performance, Low-Skew Global Network
• Architecture Supports Ultra-High UtilizationPro (Professional) I/O
• 700 Mbps DDR, LVDS-Capable I/Os
• 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation
• Bank-Selectable I/O Voltages—up to 8 Banks per Chip
• Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V / 2.5 V / 1.8 V / 1.5 V, 3.3 V PCI / 3.3 V PCI-X, and LVCMOS 2.5 V / 5.0 V Input
• Differential I/O Standards: LVPECL, LVDS, B-LVDS, and M-LVDS
• Voltage-Referenced I/O Standards: GTL+ 2.5 V / 3.3 V, GTL 2.5 V / 3.3 V, HSTL Class I and II, SSTL2 Class I and II, SSTL3 Class I and II
• I/O Registers on Input, Output, and Enable Paths
• Hot-Swappable and Cold Sparing I/Os
• Programmable Output Slew Rate and Drive Strength
• Programmable Input Delay
• Schmitt Trigger Option on Single-Ended Inputs
• Weak Pull-Up/-Down
• IEEE 1149.1 (JTAG) Boundary Scan Test
• Pin-Compatible Packages across the ProASIC®3E FamilyClock Conditioning Circuit (CCC) and PLL
• Six CCC Blocks, Each with an Integrated PLL
• Configurable Phase-Shift, Multiply/Divide, Delay Capabilities and External Feedback
• Wide Input Frequency Range (1.5 MHz to 350 MHz)SRAMs and FIFOs
• Variable-Aspect-Ratio 4,608-Bit RAM Blocks (×1, ×2, ×4, ×9, and ×18 organizations available)
• True Dual-Port SRAM (except ×18)
• 24 SRAM and FIFO Configurations with Synchronous Operation up to 350 MHzARM® Processor Support in ProASIC3E FPGAs
• M1 ProASIC3E Devices—Cortex-M1 Soft Processor Available with or without Debug
Functional Equivalent (FE) materials, including Fused Filament Fabrication (FFF) form, assembly, and functionally compatible substitute materials.
SHIPPING GUIDE
Shipping Methods
Rest assured that your orders will be handled by these trusted providers, such as DHL, FedEx, SF, and UPS.
Shipping Cost
Shipping starts at $40 but varies for destinations like South Africa, Brazil, India, and more. The actual shipping charges depend on time zone, country, and package weight/volume.
Delivery Time
We ship orders once daily, around 5 p.m., except on Sundays. The estimated delivery time may vary depending on the courier service you choose, but typically ranges from 5 to 7 business days.
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