DP83867CSRGZR

DP83816AVNG Description  
The Texas Instruments DP83816AVNG is a single-chip Ethernet IC for those low-cost, high-capacity PC motherboards, adapter cards, and embedded systems.
The DP83816AVNG supports full-duplex 10/100Mb/s transmission and reception with minimal inter-frame gaps.
The DP83816AVNG is specified Operating temperature from 0°C to 70°C.   DP83816AVNG
Features   · IEEE 802.3 Compliant， PC IV 2.2MAC/BIU supports traditional data rates of 10Mb/s Ethernet and 100Mb/s FastEthernet(via internal phy)· Busmaster-burst sizes of upto128d words ( 512 bytes)· BIU compliant with PC97andPC 98 Hardware Design Guides， PC 99 Hardware Design Guide draft， ACPI v 1.0，PCI Power Management Specification v 1.1， On Now Device Class Power Management Reference Specification-Network Device Class v 1.0a· Wake on LAN(WOL) support compliant with PC 98，PC 99， Secure On， and On Now， including directed packets， Magic Packet， VLAN packets， ARP packets，pattern match packets， and Phy status change· Clk run function for PCI Mobile Design Guide· Virtual LAN(VLAN) and long frame support· Support for IEEE 802.3x Full duplex flowcontrol· Extremely flexible Rx packet filtration including：single address perfect filter with MSb masking， broadcast， 512 entry multicast/unicast hashtable， deep packet pattern matching for up to 4 unique patterns· Statistics gathered for support of RFC 1213(MIB II) ， RFC 1398(Ether-like MIB) ， IEEE 802.3LME， reducing CPU overhead for management· Internal 2KBTransmitand2KB Receive data FIFOs· Serial EEPROM port with auto-load of configuration data from EEPROM at power-on· Flash/PROM interface for remote boot support· Fully integrated IEEE 802.3/802.3u 3.3VCMOS physical layer· IEEE 802.310BASE-T transceiver with integrated filters· IEEE 802.3u100BASE-TX transceiver· Fully integrated AN SIX 3.263 compliant TP-PMD physical sublayer with adaptive equalization and Baseline Wander compensation· IEEE 802.3uAu to-Negotiation-advertised features configurable via EEPROM· Full Duplex support for 10and100Mb/s data rates· Single 25MHz reference clock· 144-pin LQFP package· Low power 3.3VCMOS design with typical consumption of 383mW operating， 297mWduringWOLand53mW during sleep mode· IEEE 802.3uMII for connecting alternative external Physical Layer Devices· 3.3Vsignallingwith5V tolerant I/O   DP83816AVNG Applications   · Information Communication· Automotive Electronics· Consumer Electronics· Industrial Control