Image is for your reference only, please check specifications for details
iconCompare
icon

EPC2LC20

  • In Stock: 1000
  • Available: 2790

Reference Price(In US Dollars)

QtyUnit PriceExt.Price
1+US $3.60000US $3.60
10+US $3.24000US $32.40
30+US $2.52000US $75.60
100+US $2.07000US $207.00
500+US $1.98000US $990.00
1000+US $1.80000US $1800.00

Do you want a lower wholesale price? Please send us an inquiry, and we will respond immediately.

Quick RFQ
  • esd
  • as
  • iso14001
  • iso9001
  • D&B
  • Description
  • Alternatives
  • Shopping Guide
Description
Functional DescriptionWith SRAM-based devices, configuration data must be reloaded each time the device powers up, the system initializes, or when new configuration data is needed. Altera configuration devices store configuration data for SRAM-based ACEX 1K, APEX 20K, APEX II, Arria GX, Cyclone, Cyclone II, FLEX 10K, FLEX 6000, Mercury, Stratix, Stratix GX, Stratix II, and Stratix II GX devices.
FeaturesConfiguration devices for SRAM-based LUT devices offer the following features:
• Configures Altera ACEX® 1K, APEX® 20K (including APEX 20K, APEX 20KC, and APEX 20KE), APEX II, Arria® GX, Cyclone®, Cyclone II, FLEX® 10K (including FLEX 10KE and FLEX 10KA) Mercury®, Stratix®, Stratix GX, Stratix II, and Stratix II GX devices
• Easy-to-use four-pin interface
• Low current during configuration and near-zero standby mode current
• Programming support with the Altera Programming Unit (APU) and programming hardware from Data I/O, BP Microsystems, and other third-party programmers
• Available in compact plastic packages
• 8-pin plastic dual in-line (PDIP) package
• 20-pin plastic J-lead chip carrier (PLCC) package
• 32-pin plastic thin quad flat pack (TQFP) package
• EPC2 device has reprogrammable flash configuration memory
• 5.0-V and 3.3-V in-system programmability (ISP) through the built-in IEEE Std.1149.1 JTAG interface
• Built-in JTAG boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1
• Supports programming through Serial Vector Format File (.svf), Jam Standard Test and Programming Language (STAPL) Format File (.jam), JAM Byte Code File (.jbc), and the Quartus II and MAX+PLUS II softwares using the USB-Blaster, MasterBlaster®, ByteBlaster® II, EthernetBlaster, or ByteBlasterMV® download cable
• Supports programming through Programmer Object File (.pof) for EPC1 and EPC1441 devices
• nINIT_CONF pin allows INIT_CONF JTAG instruction to begin FPGA configuration
Alternatives

Functional Equivalent (FE) materials, including Fused Filament Fabrication (FFF) form, assembly, and functionally compatible substitute materials.

SHIPPING GUIDE

  • Shipping Methods

    Rest assured that your orders will be handled by these trusted providers, such as DHL, FedEx, SF, and UPS.

  • Shipping Cost

    Shipping starts at $40 but varies for destinations like South Africa, Brazil, India, and more. The actual shipping charges depend on time zone, country, and package weight/volume.

  • Delivery Time

    We ship orders once daily, around 5 p.m., except on Sundays. The estimated delivery time may vary depending on the courier service you choose, but typically ranges from 5 to 7 business days.

  • Professional Platform

  • Full-speed Delivery

  • Wide Variety of Products

  • 365 Days of Quality Assurance