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EPM7160STI100-10N

  • In Stock: 1000
  • Available: 11668
  • Updated: 13 HRS ago

Reference Price(In US Dollars)

QtyUnit PriceExt.Price
1+US $743.88600US $743.89
10+US $644.70120US $6447.01
30+US $585.19032US $17555.71
100+US $535.59792US $53559.79
500+US $520.72020US $260360.10
1000+US $495.92400US $495924.00

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  • Description
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Description
EPM7160STI100-10N Description EPM7160STI100-10N are CPLD - Complex Programmable Logic Devices.
The MAX 7000 family of high-density, high-performance PLDs is based on Altera’s second-generation MAX architecture. Fabricated with advanced CMOS technology, the EEPROM-based MAX 7000 family provides 600 to 5,000 usable gates, ISP, pin-to-pin delays as fast as 5 ns, and counter speeds of up to 175.4 MHz.  EPM7160STI100-10N
Features
• High-performance, EEPROM-based programmable logic devices (PLDs) based on second-generation MAX® architecture
• 5.0-V in-system programmability (ISP) through the built-in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface available in MAX 7000S devices– ISP circuitry compatible with IEEE Std. 1532
• Includes 5.0-V MAX 7000 devices and 5.0-V ISP-based MAX 7000S devices
• Built-in JTAG boundary-scan test (BST) circuitry in MAX7000S devices with 128 or more macrocells
• Complete EPLD family with logic densities ranging from 600 to 5,000 usable gates (see Tables 1 and 2)
• 5-ns pin-to-pin logic delays with up to 175.4-MHz counter frequencies (including interconnect)
• PCI-compliant devices available
Alternatives

Functional Equivalent (FE) materials, including Fused Filament Fabrication (FFF) form, assembly, and functionally compatible substitute materials.

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