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GTLP6C817MTC

  • Available: 13248

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Description

The GTLP6C817 is a low drive clock driver that provides TTL to GTLP signal level translation (and vice versa).
The device provides a high speed interface between cards operating at TTL logic levels and a backplane operating at GTLP logic levels. High speed backplane operation is a direct result of GTLP’s reduced output swing (<1V), reduced input threshold levels and output edge rate control.
The edge rate control minimizes bus settling time. GTLP is a Fairchild Semiconductor derivative of the Gunning Transceiver logic (GTL) JEDEC standard JESD8-3.
Features
• Interface between TTL and GTLP logic levels
• Edge Rate Control to minimize noise on the GTLP port
• Power up/down high impedance for live insertion
• 1:6 fanout clock driver for LVTTL port
• 1:2 fanout clock driver for GTLP port
• LVTTL compatible driver and control inputs
• 5V over voltage tolerance on LVTTL ports
• Flow through pinout optimizes PCB layout
• Open drain on GTLP to support wired-or connection
• Recommended Operating Temperature −40°C to +85°C
Alternatives

Functional Equivalent (FE) materials, including Fused Filament Fabrication (FFF) form, assembly, and functionally compatible substitute materials.

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