ISPLSI 2064A-100LT100

Description
The ispLSI 2032 and 2032A are High Density Programmable Logic Devices.
The devices contain 32 Registers, 32 Universal I/O pins, two Dedicated Input Pins, three Dedicated Clock Input Pins, one dedicated Global OE input pin and a Global Routing Pool (GRP).
The GRP provides complete interconnectivity between all of these elements.
The ispLSI 2032 and 2032A feature 5V in system programmability and in-system diagnostic capabilities.
The ispLSI 2032 and 2032A offer nonvolatile reprogrammability of the logic, as well as the interconnect to provide truly reconfigurable systems.
Features
• ENHANCEMENTS — ispLSI 2032A is Fully Form and Function Compat to the ispLSI 2032, with Identical Timing Specifcations and Packaging — ispLSI 2032A is Built on an Advanced 0.35 Micron E2CMOS® Technology
• HIGH DENSITY PROGRAMMABLE LOGIC — 1000 PLD Gates — 32 I/O Pins, Two Dedicated Inputs — 32 Registers — High Speed Global Interconnect — Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc. — Small Logic Block Size for Random Logic
• HIGH PERFORMANCE E2CMOS® TECHNOLOGY — fmax = 180 MHz Maximum Operating Frequency — tpd = 5.0 ns Propagation Delay — TTL Compatible Inputs and Outputs — Electrically Erasable and Reprogrammable — Non-Volatile — 100% Tested at Time of Manufacture — Unused Product Term Shutdown Saves Power
• IN-SYSTEM PROGRAMMABLE — In-System Programmable (ISP™) 5V Only — Increased Manufacturing Yields, Reduced Time-to Market and Improved Product Quality — Reprogram Soldered Devices for Faster Prototyp
• OFFERS THE EASE OF USE AND FAST SYSTEM SPEED OF PLDs WITH THE DENSITY AND FLEXIBIL OF FIELD PROGRAMMABLE GATE ARRAYS — Complete Programmable Device Can Combine G Logic and Structured Designs — Enhanced Pin Locking Capability — Three Dedicated Clock Input Pins — Synchronous and Asynchronous Clocks — Programmable Output Slew Rate Control to Minimize Switching Noise — Flexible Pin Placement — Optimized Global Routing Pool Provides Global Interconnectivity