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MC10E195FNR2

  • Available: 7135

Reference Price(In US Dollars)

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Description

The MC10E/100E195 is a programmable delay chip (PDC) designed primarily for clock de-skewing and timing adjustment. It provides variable delay of a differential ECL input transition.
Features
• 2.0 ns Worst Case Delay Range
• ≈20 ps/Delay Step Resolution
• >1.0 GHz Bandwidth
• On Chip Cascade Circuitry
• PECL Mode Operating Range: VCC = 4.2 V to 5.7 V with VEE = 0 V
• NECL Mode Operating Range: VCC = 0 V with VEE = −4.2 V to −5.7 V
• Internal Input 50 kΩ Pulldown Resistors
• ESD Protection: Human Body Model; > 2 kV, Machine Model; > 200 V
• Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
• Moisture Sensitivity Level: Pb = 1; Pb−Free = 3For Additional Information, see Application Note AND8003/D
• Flammability Rating: UL 94 V−0 @ 0.125 in, Oxygen Index: 28 to 34
• Transistor Count = 368 devices
• Pb−Free Packages are Available
*
Alternatives

Functional Equivalent (FE) materials, including Fused Filament Fabrication (FFF) form, assembly, and functionally compatible substitute materials.

SHIPPING GUIDE

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