PAL22V10Z-25CJTL

PAL22V10Z-25CJTL Description
The PAL22V10Z-25CJTL power factor correction is rated for temperatures ranging from 0°C to 75°C. Power factor correction is the process of compensating for lagging current by creating a leading current by connecting capacitors to the supply.
The PAL22V10Z-25CJTL includes a programmable design security cell for design security. When this cell is programmed, the readverify and programming circuitry is disabled, preventing the design from being copied. PAL22V10Z-25CJTL
Features
• 24-Pin Advanced CMOS PLD
• Virtually Zero Standby Power
• Propagation Delay Time:I, I/O to I/O in the Turbo Mode-25C  .  .  .  25 ns Max-30I  .  .  .  30 ns MaxI, I/O to I/O in the Zero-Power Mode-25C  .  .  .  35 ns Max-30I  .  .  .  40 ns MaxCLK to Q-25C  .  .  .  15 ns Max-30I  .  .  .  20 ns Max
• Variable Product Term Distribution AllowsMore Complex Functions to BeImplemented
• Each Output Is User-Programmable forRegistered or Combinatorial Operation,Polarity, and Output Enable Control
• Extra Terms Provide Logical SynchronousSet and Asynchronous Reset Capability
• Preload Capability on All RegisteredOutputs Allow for Improved Device Testing
• UV Light Erasable Cell Technology Allowsfor:Reconfigurable LogicReprogrammable CellsFull Factory Testing for HighProgramming Yield
• Programmable Design Security Bit Prevents Copying of Logic Stored in Device
• Package Options Include Plastic Dual-In-Line and Clip Carrier [for One-Time-Programmable (OTP) Devices] and Ceramic Dual-In-Line Windowed Package PAL22V10Z-25CJTL Applications
• Lighting
• PC Power
• High-power applications
• Consumer Electronics
• Industrial Power Supplies