TIBPAL22V10ACNT

Description
The TIBPAL22V10-5C is a programmable array logic device featuring high speed and functional equivalency when compared to presently available devices.
The TIBPAL22V10-5C is implemented with the familiar sum-of-products (AND-OR) logic structure featuring programmable output logic macrocells.
These IMPACT-XL circuits combine the latest Advanced Low-Power Schottky technology with proven titaniumtungsten fuses to provide reliable, high-performance substitutes for conventional TTL logic. This device contains up to 22 inputs and 10 outputs. It incorporates the unique capability of defining and programming the architecture of each output on an individual basis. Outputs can be registered or nonregistered and inverting or noninverting as shown in the output logic macrocell diagram.
The ten potential outputs are enabled through the use of individual product terms. Further advantages can be seen in the introduction of variable product term distribution. This technique allocates from 8 to 16 logical product terms to each output for an average of 12 product terms per output. This variable allocation of terms allows far more complex functions to be implemented than in previously available devices.   Circuit design is enhanced by the addition of a synchronous set and an asynchronous reset product term.
These functions are common to all registers. When the synchronous set product term is a logic 1, the output registers are loaded with a logic 1 on the next low-to high clock transition. When the asynchronous reset product term is a logic 1, the output registers are loaded with a logic 0.
The output logic level after set or reset depends on the polarity selected during programming. Output registers can be preloaded to any desired state during testing. Preloading permits full logical verification during product testing. With features such as programmable output logic macrocells and variable product term distribution, the TIBPAL22V10-5C offers quick design and development of custom LSI functions with complexities of 500 to 800 equivalent gates. Since each of the ten output pins can be individually configured as inputs on either a temporary or permanent basis, functions requiring up to 21 inputs and a single output or down to 12 inputs and 10 outputs are possible. A power-up clear function is supplied that forces all registered outputs to a predetermined state after power is applied to the device. Registered outputs selected as active-low power up with their outputs high. Registered outputs selected as active-high power up with their outputs low. A single security fuse is provided on each device to discourage unauthorized copying of fuse patterns. Once blown, the verification circuitry is disabled and all other fuses will verify as open.
The TIBPAL22V10-5C is characterized for operation from 0°C to 75°C.  
Features
• High-Performance Operation: fmax (External Feedback) . . . 117 MHz Propagation Delay . . . 5 ns Max
• Increased Logic Power
– Up to 22 Inputs and 10 Outputs
• Increased Product Terms
– Average of 12 Per Output
• Variable Product Term Distribution Allows More Complex Functions to Be Implemented
• Each Output Is User Programmable for Registered or Combinational Operation, Polarity, and Output Enable Control
• Power-Up Clear on Registered Outputs
• TTL-Level Preload for Improved Testability
• Extra Terms Provide Logical Synchronous Set and Asynchronous Reset Capability
• Fast Programming, High Programming Yield, and Unsurpassed Reliability Ensured Using Ti-W Fuses
• AC and DC Testing Done at the Factory Utilizing Special Designed-In Test
Features
• JEDEC Approved Revolutionary Power and Ground Pinout for 28-Pin Chip Carrier Reduces Cross Talk and Ground Bounce
• JEDEC File Compatibility Allows Previous ’22V10 Designs to be Programmed Into the TIBPAL22V10-5C Without Modifications