TMSDM6467TCUT1TAN

TMSDM6467TCUT1TAN Description
The TMSDM6467TCUT1TAN DSP processor has application-specific hardware logic, on-chip memory, and additional on-chip peripherals similar to the other DSP platform devices.
The TMSDM6467TCUT1TAN core uses a two-level cachebased architecture.
The Level 1 program cache (L1P) is a 256K-bit direct mapped cache and the Level 1 data cache (L1D) is a 640K-bit 2-way set-associative cache.
The Level 2 memory/cache (L2) consists of an 512K-bit memory space that is shared between program and data space. TMSDM6467TCUT1TAN
Features
• USB Port With Integrated 2.0 PHY– USB 2.0 High-/Full-Speed Client– USB 2.0 High-/Full-/Low-Speed Host(Mini-Host, Supporting One External Device)
• Enhanced Direct-Memory-Access (EDMA) Controller (64 Independent Channels)– Programmable Default Burst Size
• External Memory Interfaces (EMIFs)– Up to 400-MHz 32-Bit DDR2 SDRAM Memory Controller With 512M-Byte Address Space– Asynchronous16-Bit Wide EMIF (EMIFA) With 128M-Byte Address Reach
• Two Transport Stream Interface (TSIF) Modules– TSIF for MPEG Transport Stream– Simultaneous Synchronous or Asynchronous Input/Output Streams TMSDM6467TCUT1TAN Applications
• Video Conferencing
• Video Infrastructure
• Video Imaging 
• Networked Media Encode/Decode 
• Digital Media 
• Video Encode/Decode/Transcode/Transrate