XC2C512-10PQG208C
- Manufacturer's Part No.:XC2C512-10PQG208C
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- Series:CoolRunner II
- Description:IC CPLD 512MC 9.2NS 208QFP
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- Available: 375
Reference Price(In US Dollars)
Qty | Unit Price | Ext.Price |
---|---|---|
1+ | US $97.14600 | US $97.15 |
10+ | US $75.55800 | US $755.58 |
30+ | US $64.76400 | US $1942.92 |
100+ | US $59.36700 | US $5936.70 |
500+ | US $57.20820 | US $28604.10 |
1000+ | US $53.97000 | US $53970.00 |
Do you want a lower wholesale price? Please send us an inquiry, and we will respond immediately.
- Description
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The Xilinx XC2C512-10PQG208C is one of the CoolRunner-II CPLDs with all the advanced features of the CoolRunner™-II.
The XC2C512-10PQG208C can be used in a PQFP-208 enclosure with a reference supply voltage of 1.7V minimum and 1.9V maximum. XC2C512-10PQG208C
Features
• Design entry/verification using Xilinx and industry standard CAE tools
• Free software support for all densities using Xilinx® WebPACK™ tool
• Optimized for 1.8V systems- Industry’s fastest low power CPLD- Densities from 32 to 512 macrocells
• Industry’s best 0.18 micron CMOS CPLD- Optimized architecture for effective logic synthesis - Multi-voltage I/O operation — 1.5V to 3.3V
• PLA architecture- Superior pinout retention- 100% product term routability across function block
• Wide package availability including fine pitch:- Chip Scale Package (CSP) BGA, Fine Line BGA, TQFP, PQFP, VQFP, and QFN packages- Pb-free available for all packages
• Advanced system features- Fastest in system programming · 1.8V ISP using IEEE 1532 (JTAG) interface- On-
The-Fly Reconfiguration (OTF)- IEEE1149.1 JTAG Boundary Scan Test- Optional Schmitt trigger input (per pin)- Multiple I/O banks on all devices- Unsurpassed low power management · DataGATE external signal control- Flexible clocking modes · Optional DualEDGE triggered registers · Clock divider (÷ 2,4,6,8,10,12,14,16) · CoolCLOCK - Global signal options with macrocell control · Multiple global clocks with phase selection per macrocell · Multiple global output enables· Global set/reset - Abundant product term clocks, output enables and set/resets- Efficient control term clocks, output enables and set/resets for each macrocell and shared across function blocks- Advanced design security- Open-drain output option for Wired-OR and LED drive- Optional bus-hold, 3-state or weak pullup on select I/O pins- Optional configurable grounds on unused I/Os- Mixed I/O voltages compatible with 1.5V, 1.8V, 2.5V, and 3.3V logic levels on all parts- SSTL2_1,SSTL3_1, and HSTL_1 on 128 macrocell and denser devices- Hot pluggable XC2C512-10PQG208C Applications
• High-speed data communications
• Computing systems
• Portable products
Functional Equivalent (FE) materials, including Fused Filament Fabrication (FFF) form, assembly, and functionally compatible substitute materials.
SHIPPING GUIDE
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Shipping Cost
Shipping starts at $40 but varies for destinations like South Africa, Brazil, India, and more. The actual shipping charges depend on time zone, country, and package weight/volume.
Delivery Time
We ship orders once daily, around 5 p.m., except on Sundays. The estimated delivery time may vary depending on the courier service you choose, but typically ranges from 5 to 7 business days.
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