XC7Z020-1CLG484I

Description
The ZynqR-7000 family is based on the Xilinx SoC architecture. 1
These products integrate a feature-rich dual-core or single-core ARM@ CortexTM-A9 based processing system (PS) and 28 nm Xilinx programmable logic (PL) in a single device.
The ARM Cortex-A9 CPUs are the heart of the PS and also include on-chip memory, extemal memory interfaces, and a rich set of peripheral connectivity interfaces.  
Features
• Dual-core or single-core ARM Cortex-A9 MPCores.
Features associated with each core include:
• 2.5 DMIPS/MHz
• Operating frequency range:- Z-7007S/Z-7012S/Z-7014S (wire bond): Up to 667 MHz (-1); 766 MHz (-2)- Z-7010/Z-7015/Z-7020 (wire bond): Up to 667 MHz (-1); 766 MHz (-2); 866 MHz (-3)- Z-7030/Z-7035/Z-7045 (flip-chip): 667 MHz (-1); 800 MHz (-2); 1GHz (-3)- Z-7100 (flip-chip): 667 MHz (-1); 800 MHz (-2)
• Ability to operate in single processor, symmetric dual processor, and asymmetric dual processor modes
• Single and double precision floating point: up to 2.0 MFLOPS/MHz each
• NEON media processing engine for SIMD support
• Thumb®-2 support for code compression
• Level 1 caches (separate instruction and data, 32 KB each)- 4-way set-associative- Non-blocking data cache with support for up to four outstanding read and write misses each
• Integrated memory management unit (MMU)
• TrustZone® for secure mode operation
• Accelerator coherency port (ACP) interface enabling coherent accesses from PL to CPU memory space
• Unified Level 2 cache (512 KB)
• 8-way set-associative
• TrustZone enabled for secure operation
• Dual-ported, on-chip RAM (256 KB)
• Accessible by CPU and programmable logic (PL)
• Designed for low latency access from the CPU
• 8-channel DMA
• Supports multiple transfer types: memory-to-memory, memory-to-peripheral, peripheral-to-memory, and scatter-gather
• 64-bit AXI interface, enabling high throughput DMA transfers
• 4 channels dedicated to PL
• TrustZone enabled for secure operation
• Dual register access interfaces enforce separation between secure and non-secure accesses
• Interrupts and Timers
• General interrupt controller (GIC)
• Three watch dog timers (WDT) (one per CPU and one system WDT)
• Two triple timers/counters (TTC)
• CoreSight debug and trace support for Cortex-A9
• Program trace macrocell (PTM) for instruction and trace
• Cross trigger interface (CTI) enabling hardware breakpoints and triggers   Applications
• Automotive driver assistance, driver information, and infotainment
• Broadcast camera
• Industrial motor control, industrial networking, and machine vision
• IP and Smart camera
• LTE radio and baseband
• Medical diagnostics and imaging
• Multifunction printers
• Video and night vision equipment