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ZL30407QCG1

  • Available: 10885

Reference Price(In US Dollars)

QtyUnit PriceExt.Price
1+US $0.00000US $0.00

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  • Description
  • Alternatives
  • Shopping Guide
Description

The ZL30406 is an analog phase-locked loop (APLL) designed to provide rate conversion and jitter attenuation for SDH (Synchronous Digital Hierarchy) and SONET (Synchronous Optical Network) networking equipment.
The ZL30406 generates very low jitter clocks that meet the jitter requirements of Telcordia GR-253-CORE OC-48, OC-12, OC-3, OC-1 rates and ITU-T G.813 STM-16, STM-4 and STM-1 rates.
Features
• Meets jitter requirements of Telcordia GR-253-CORE for OC-48, OC-12, and OC-3 rates
• Meets jitter requirements of ITU-T G.813 for STM-16, STM-4 and STM-1 rates
• Provides four LVPECL differential output clocks at 77.76 MHz
• Provides a CML differential clock programmableto 19.44 MHz, 38.88 MHz, 77.76 MHz and 155.52 MHz
• Provides a single-ended CMOS clock at 19.44 MHz
• Provides enable/disable control of output clocks
• Accepts a CMOS reference at 19.44 MHz
• 3.3 V supplyApplications
• SONET/SDH line cards
• Network Element timing cards
Alternatives

Functional Equivalent (FE) materials, including Fused Filament Fabrication (FFF) form, assembly, and functionally compatible substitute materials.

SHIPPING GUIDE

  • Shipping Methods

    Rest assured that your orders will be handled by these trusted providers, such as DHL, FedEx, SF, and UPS.

  • Shipping Cost

    Shipping starts at $40 but varies for destinations like South Africa, Brazil, India, and more. The actual shipping charges depend on time zone, country, and package weight/volume.

  • Delivery Time

    We ship orders once daily, around 5 p.m., except on Sundays. The estimated delivery time may vary depending on the courier service you choose, but typically ranges from 5 to 7 business days.

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