![](/images/home/default.png)
![icon](/images/products/arrowIcon.webp)
![icon](/images/products/fsr.webp)
A3P125-1FGG144I
- Manufacturer's Part No.:A3P125-1FGG144I
- Manufacturer:
- Categories:
- Sub-Categories:
- Series:ProASIC3
- Description:IC FPGA 97 I/O 144FBGA
- Datasheet:
- Quantity:RFQAdd to RFQ List
- Payment:
- Delivery:
- In Stock: 5901
- Available: 5901
Reference Price(In US Dollars)
Qty | Unit Price | Ext.Price |
---|---|---|
1+ | US $31.68800 | US $31.69 |
10+ | US $23.76600 | US $237.66 |
30+ | US $20.59720 | US $617.92 |
100+ | US $18.22060 | US $1822.06 |
500+ | US $17.11152 | US $8555.76 |
1000+ | US $15.84400 | US $15844.00 |
Do you want a lower wholesale price? Please send us an inquiry, and we will respond immediately.
- Description
- Alternatives
- Shopping Guide
These features enable designers to create high-density systems using existing ASIC or FPGA design flows and tools.
Features and BenefitsHigh Capacity
• 15 k to 1 M System Gates
• Up to 144 kbits of True Dual-Port SRAM
• Up to 300 User I/OsReprogrammable Flash Technology
• 130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS Process
• Live at Power-Up (LAPU) Level 0 Support
• Single-Chip Solution
• Retains Programmed Design when Powered OffHigh Performance
• 350 MHz System Performance
• 3.3 V, 66 MHz 64-Bit PCI†In-System Programming (ISP) and Security
• Secure ISP Using On-Chip 128-Bit Advanced Encryption Standard (AES) Decryption (except ARM-enabled ProASIC®3 devices) via JTAG (IEEE 1532–compliant)†
• FlashLock® to Secure FPGA ContentsLow Power
• Core Voltage for Low Power
• Support for 1.5 V-Only Systems
• Low-Impedance Flash SwitchesHigh-Performance Routing Hierarchy
• Segmented, Hierarchical Routing and Clock StructureAdvanced I/O
• 700 Mbps DDR, LVDS-Capable I/Os (A3P250 and above)
• 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation
• Bank-Selectable I/O Voltages—up to 4 Banks per Chip
• Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V / 2.5 V / 1.8 V / 1.5 V, 3.3 V PCI / 3.3 V PCI-X† and LVCMOS 2.5 V / 5.0 V Input
• Differential I/O Standards: LVPECL, LVDS, B-LVDS, and M-LVDS (A3P250 and above)
• I/O Registers on Input, Output, and Enable Paths
• Hot-Swappable and Cold Sparing I/Os‡
• Programmable Output Slew Rate† and Drive Strength
• Weak Pull-Up/-Down
• IEEE 1149.1 (JTAG) Boundary Scan Test
• Pin-Compatible Packages across the ProASIC3 FamilyClock Conditioning Circuit (CCC) and PLL†
• Six CCC Blocks, One with an Integrated PLL
• Configurable Phase-Shift, Multiply/Divide, Delay Capabilities and External Feedback
• Wide Input Frequency Range (1.5 MHz to 350 MHz)Embedded Memory†
• 1 kbit of FlashROM User Nonvolatile Memory
• SRAMs and FIFOs with Variable-Aspect-Ratio 4,608-Bit RAM Blocks (×1, ×2, ×4, ×9, and ×18 organizations)†
• True Dual-Port SRAM (except ×18)ARM Processor Support in ProASIC3 FPGAs
• M1 and M7 ProASIC3 Devices—Cortex-M1 and CoreMP7 Soft Processor Available with or without Debug
Functional Equivalent (FE) materials, including Fused Filament Fabrication (FFF) form, assembly, and functionally compatible substitute materials.
SHIPPING GUIDE
Shipping Methods
Rest assured that your orders will be handled by these trusted providers, such as DHL, FedEx, SF, and UPS.
Shipping Cost
Shipping starts at $40 but varies for destinations like South Africa, Brazil, India, and more. The actual shipping charges depend on time zone, country, and package weight/volume.
Delivery Time
We ship orders once daily, around 5 p.m., except on Sundays. The estimated delivery time may vary depending on the courier service you choose, but typically ranges from 5 to 7 business days.
RELEVANT BLOGS & POSTS
Professional Platform
Full-speed Delivery
Wide Variety of Products
365 Days of Quality Assurance