LC4064ZE-5TN100I

Features
• High Performance
• fMAX = 260MHz maximum operating frequency
• tPD = 4.4ns propagation delay
• Up to four global clock pins with programmable clock polarity control
• Up to 80 PTs per output
• Ease of Design
• Flexible CPLD macrocells with individual clock, reset, preset and clock enable controls
• Up to four global OE controls
• Individual local OE control per I/O pin
• Excellent First-Time-FitTM and refit
• Wide input gating (36 input logic blocks) for fast counters, state machines and address decoders
• Ultra Low Power
• Standby current as low as 10µA typical
• 1.8V core; low dynamic power
• Operational down to 1.6V VCC
• Superior solution for power sensitive consumer applications
• Per pin pull-up, pull-down or bus keeper control
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• Power Guard with multiple enable signals
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• Broad Device Offering
• 32 to 256 macrocells
• Multiple temperature range support
– Commercial: 0 to 90°C junction (Tj)
– Industrial: -40 to 105°C junction (Tj)
• Space-saving packages
• Easy System Integration
• Operation with 3.3V, 2.5V, 1.8V or 1.5V LVCMOS I/O
• 5V tolerant I/O for LVCMOS 3.3, LVTTL, and PCI interfaces
• Hot-socketing support
• Open-drain output option
• Programmable output slew rate
• 3.3V PCI compatible
• I/O pins with fast setup path
• Input hysteresis
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• 1.8V core power supply
• IEEE 1149.1 boundary scan testable
• IEEE 1532 ISC compliant
• 1.8V In-System Programmable (ISP™) using Boundary Scan Test Access Port (TAP)
• Pb-free package options (only)
• On-chip user oscillator and timer
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